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Very bad noise on OpenElec, Pi3 and HifiBerry Digi+

Hi, I just receive my HifiBerry Digi + today. Plug it and change the config.txt file to load the moduyle. Then in OpenElec I can select it as playback and passthrough. But when selected, I got a very big background noise. I barely hear the song when changing menu, but the noise is terrible. I try every setting on OpenElec. Can it by the Receiver that do not support it? I got a  old Sony STR-KLS7. Before the addition of HifiBerry, the 5.1 chanel are correctly decoded with passthrough set at ON and output it on HDMI to TV then to the decoder. Movies in AC3 working well with that setup. But movies in AAC give only backgroung sound. On the web I read that is because my LG TV do not let the passthrough go on the decoder with AAC.

That why I try the hifiBerry tu bypass the TV and output encoded audio directly to the decoder. DO you thing the STR-KLS7 support AC3, AAC and DTS?

I try to disable DTS, AC3 but the noise style there. I read some post telling that some incompatibility with OpenElec? Do I need to use Kodi? 

Here the log:

OpenELEC:~ # vcdbg log msg
001103.479: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
001103.515: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
001103.553: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
001103.588: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
001103.628: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
001103.661: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
001115.704: HDMI:EDID version 1.3, 1 extensions, screen size 115x65 cm
001115.769: HDMI:EDID features - videodef 0x80 !standby !suspend !active off; colour encoding:RGB444|YCbCr422; sRGB is not default colourspace; preferred format is native; does not support GTF
001115.824: HDMI:EDID found preferred CEA detail timing format: 1920x1080p @ 60 Hz (16)
001115.889: HDMI:EDID found DMT detail timing format: 1360x768p @ 60 Hz (39)
001115.930: HDMI:EDID found DMT format: code 4, 640x480p @ 60 Hz in established timing I/II
001115.968: HDMI:EDID found DMT format: code 5, 640x480p @ 72 Hz in established timing I/II
001116.005: HDMI:EDID found DMT format: code 6, 640x480p @ 75 Hz in established timing I/II
001116.044: HDMI:EDID found DMT format: code 8, 800x600p @ 56 Hz in established timing I/II
001116.079: HDMI:EDID found DMT format: code 9, 800x600p @ 60 Hz in established timing I/II
001116.117: HDMI:EDID found DMT format: code 10, 800x600p @ 72 Hz in established timing I/II
001116.154: HDMI:EDID found DMT format: code 11, 800x600p @ 75 Hz in established timing I/II
001116.193: HDMI:EDID found DMT format: code 16, 1024x768p @ 60 Hz in established timing I/II
001116.230: HDMI:EDID found DMT format: code 17, 1024x768p @ 70 Hz in established timing I/II
001116.269: HDMI:EDID found DMT format: code 18, 1024x768p @ 75 Hz in established timing I/II
001116.308: HDMI:EDID found DMT format: code 36, 1280x1024p @ 75 Hz in established timing I/II
001116.394: HDMI:EDID standard timings block x 8: 0x3140 4540 6140 8180 A940 0101 0101 0101
001116.443: HDMI:EDID found DMT format: code 4, 640x480p @ 60 Hz (4:3) in standard timing 0
001116.490: HDMI:EDID found DMT format: code 9, 800x600p @ 60 Hz (4:3) in standard timing 1
001116.538: HDMI:EDID found DMT format: code 16, 1024x768p @ 60 Hz (4:3) in standard timing 2
001116.588: HDMI:EDID found DMT format: code 35, 1280x1024p @ 60 Hz (5:4) in standard timing 3
001116.639: HDMI:EDID found DMT format: code 51, 1600x1200p @ 60 Hz (4:3) in standard timing 4
001129.645: HDMI:EDID parsing v3 CEA extension 0
001129.683: HDMI:EDID monitor support - underscan IT formats:yes, basic audio:yes, yuv444:yes, yuv422:yes, #native DTD:1
001129.724: HDMI:EDID found CEA detail timing format: 1280x720p @ 60 Hz (4)
001129.765: HDMI:EDID found CEA detail timing format: 1920x1080i @ 60 Hz (5)
001129.807: HDMI:EDID found CEA detail timing format: 720x480p @ 60 Hz (2)
001129.848: HDMI:EDID found CEA detail timing format: 720x480p @ 60 Hz (2)
001129.941: HDMI:EDID found unknown detail timing format: 1920x1080p hfp:48 hs:32 hbp:80 vfp:2 vs:5 vbp:24 pixel clock:138 MHz
001129.978: HDMI:EDID found CEA format: code 4, 1280x720p @ 60Hz (native)
001130.012: HDMI:EDID found CEA format: code 5, 1920x1080i @ 60Hz
001130.043: HDMI:EDID found CEA format: code 3, 720x480p @ 60Hz
001130.076: HDMI:EDID found CEA format: code 2, 720x480p @ 60Hz
001130.109: HDMI:EDID found CEA format: code 32, 1920x1080p @ 24Hz
001130.143: HDMI:EDID found CEA format: code 34, 1920x1080p @ 30Hz
001130.177: HDMI:EDID found CEA format: code 16, 1920x1080p @ 60Hz
001130.226: HDMI:EDID found audio format 6 channels AC3, sample rate: 32|44|48 kHz, bitrate: 640 kbps
001130.246: HDMI:EDID found HDMI VSDB length 7
001130.270: HDMI:EDID HDMI VSDB has physical address 4.0.0.0
001130.291: HDMI:EDID HDMI VSDB supports AI:yes, dual link DVI:no
001130.322: HDMI:EDID HDMI VSDB deep colour support - 48-bit:no 36-bit:yes 30-bit:yes DC_yuv444:yes
001130.342: HDMI:EDID HDMI VSDB max TMDS clock 225 MHz
001130.357: HDMI:EDID HDMI VSDB has no latency information
001130.397: HDMI:EDID filtering formats with pixel clock > 162 MHz or h. blanking > 1023
001130.585: HDMI:EDID preferred mode remained as CEA (16) 1920x1080p @ 60 Hz with pixel clock 148 MHz
001130.640: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
001130.673: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
001135.576: HDMI:Setting property pixel encoding to Default
001135.596: HDMI:Setting property pixel clock type to PAL
001135.615: HDMI:Setting property content type flag to No data
001135.634: HDMI:Setting property fuzzy format match to enabled
001154.141: clock: clock_set_clock: dst: CLK_GP1, source: PLLD_PER, div: 20.000000
001154.179: clock: clock_set_clock: dst: CLK_GP2, source: XOSC, div: 600.000000
001154.210: gpioman: gpioman_get_pin_num: pin LEDS_RUNNING not defined
001154.235: gpioman: gpioman_get_pin_num: pin LEDS_NAND_ACTIVITY not defined
001154.258: gpioman: gpioman_get_pin_num: pin LEDS_USB_ACTIVITY not defined
001154.281: gpioman: gpioman_get_pin_num: pin LEDS_FATAL_ERROR not defined
001154.301: gpioman: gpioman_get_pin_num: pin LEDS_APP_OK not defined
001154.322: gpioman: gpioman_get_pin_num: pin LEDS_APP_FAILED not defined
001154.345: gpioman: gpioman_get_pin_num: pin LEDS_HDCP_AUTH not defined
001154.365: gpioman: gpioman_get_pin_num: pin LEDS_HDCP_UNAUTH not defined
001154.385: gpioman: gpioman_get_pin_num: pin LEDS_HDMI_ON not defined
001154.406: gpioman: gpioman_get_pin_num: pin LEDS_DVI_ON not defined
001154.426: gpioman: gpioman_get_pin_num: pin LEDS_HDMI_HPD_UP not defined
001154.449: gpioman: gpioman_get_pin_num: pin LEDS_REMOTE_CONTROL not defined
001154.472: gpioman: gpioman_get_pin_num: pin LEDS_ARM_CONTROLLED not defined
001308.816: clock: Set PLLB_VCO to 640000000
001308.928: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
001308.965: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 0.000000
001309.003: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 1.000000
001309.037: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 0.000000
001309.063: clock: Set PLLB_VCO to 640000000
001309.174: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
001309.207: clock: Set PLLB_VCO to 1200000000
001309.279: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
001329.204: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 0.000000
001335.525: hdmi: HDMI:>>>>>>>>>>>>>Rx sensed, reading EDID<<<<<<<<<<<<<
001335.588: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
001335.624: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
001335.662: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
001335.697: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
001335.737: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
001335.769: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
001347.817: hdmi: HDMI:EDID version 1.3, 1 extensions, screen size 115x65 cm
001347.886: hdmi: HDMI:EDID features - videodef 0x80 !standby !suspend !active off; colour encoding:RGB444|YCbCr422; sRGB is not default colourspace; preferred format is native; does not support GTF
001347.948: hdmi: HDMI:EDID found preferred CEA detail timing format: 1920x1080p @ 60 Hz (16)
001348.018: hdmi: HDMI:EDID found DMT detail timing format: 1360x768p @ 60 Hz (39)
001348.063: hdmi: HDMI:EDID found DMT format: code 4, 640x480p @ 60 Hz in established timing I/II
001348.105: hdmi: HDMI:EDID found DMT format: code 5, 640x480p @ 72 Hz in established timing I/II
001348.145: hdmi: HDMI:EDID found DMT format: code 6, 640x480p @ 75 Hz in established timing I/II
001348.187: hdmi: HDMI:EDID found DMT format: code 8, 800x600p @ 56 Hz in established timing I/II
001348.227: hdmi: HDMI:EDID found DMT format: code 9, 800x600p @ 60 Hz in established timing I/II
001348.269: hdmi: HDMI:EDID found DMT format: code 10, 800x600p @ 72 Hz in established timing I/II
001348.309: hdmi: HDMI:EDID found DMT format: code 11, 800x600p @ 75 Hz in established timing I/II
001348.351: hdmi: HDMI:EDID found DMT format: code 16, 1024x768p @ 60 Hz in established timing I/II
001348.391: hdmi: HDMI:EDID found DMT format: code 17, 1024x768p @ 70 Hz in established timing I/II
001348.434: hdmi: HDMI:EDID found DMT format: code 18, 1024x768p @ 75 Hz in established timing I/II
001348.478: hdmi: HDMI:EDID found DMT format: code 36, 1280x1024p @ 75 Hz in established timing I/II
001348.568: hdmi: HDMI:EDID standard timings block x 8: 0x3140 4540 6140 8180 A940 0101 0101 0101
001348.621: hdmi: HDMI:EDID found DMT format: code 4, 640x480p @ 60 Hz (4:3) in standard timing 0
001348.672: hdmi: HDMI:EDID found DMT format: code 9, 800x600p @ 60 Hz (4:3) in standard timing 1
001348.723: hdmi: HDMI:EDID found DMT format: code 16, 1024x768p @ 60 Hz (4:3) in standard timing 2
001348.777: hdmi: HDMI:EDID found DMT format: code 35, 1280x1024p @ 60 Hz (5:4) in standard timing 3
001348.832: hdmi: HDMI:EDID found DMT format: code 51, 1600x1200p @ 60 Hz (4:3) in standard timing 4
001361.840: hdmi: HDMI:EDID parsing v3 CEA extension 0
001361.881: hdmi: HDMI:EDID monitor support - underscan IT formats:yes, basic audio:yes, yuv444:yes, yuv422:yes, #native DTD:1
001361.925: hdmi: HDMI:EDID found CEA detail timing format: 1280x720p @ 60 Hz (4)
001361.969: hdmi: HDMI:EDID found CEA detail timing format: 1920x1080i @ 60 Hz (5)
001362.014: hdmi: HDMI:EDID found CEA detail timing format: 720x480p @ 60 Hz (2)
001362.059: hdmi: HDMI:EDID found CEA detail timing format: 720x480p @ 60 Hz (2)
001362.158: hdmi: HDMI:EDID failed to find a matching detail format for 1920x1080p hfp:48 hs:32 hbp:80 vfp:2 vs:5 vbp:24 pixel clock:138 MHz
001362.182: hdmi: HDMI:EDID calculated refresh rate is 60 Hz
001362.215: hdmi: HDMI:EDID guessing the format to be 1920x1080p @60 Hz
001362.260: hdmi: HDMI:EDID found CEA detail timing format: 1920x1080p @ 60 Hz (16)
001362.298: hdmi: HDMI:EDID found CEA format: code 4, 1280x720p @ 60Hz (native)
001362.336: hdmi: HDMI:EDID found CEA format: code 5, 1920x1080i @ 60Hz
001362.370: hdmi: HDMI:EDID found CEA format: code 3, 720x480p @ 60Hz
001362.404: hdmi: HDMI:EDID found CEA format: code 2, 720x480p @ 60Hz
001362.441: hdmi: HDMI:EDID found CEA format: code 32, 1920x1080p @ 24Hz
001362.476: hdmi: HDMI:EDID found CEA format: code 34, 1920x1080p @ 30Hz
001362.514: hdmi: HDMI:EDID found CEA format: code 16, 1920x1080p @ 60Hz
001362.567: hdmi: HDMI:EDID found audio format 6 channels AC3, sample rate: 32|44|48 kHz, bitrate: 640 kbps
001362.590: hdmi: HDMI:EDID found HDMI VSDB length 7
001362.619: hdmi: HDMI:EDID HDMI VSDB has physical address 4.0.0.0
001362.643: hdmi: HDMI:EDID HDMI VSDB supports AI:yes, dual link DVI:no
001362.676: hdmi: HDMI:EDID HDMI VSDB deep colour support - 48-bit:no 36-bit:yes 30-bit:yes DC_yuv444:yes
001362.699: hdmi: HDMI:EDID HDMI VSDB max TMDS clock 225 MHz
001362.718: hdmi: HDMI:EDID HDMI VSDB has no latency information
001362.761: hdmi: HDMI:EDID filtering formats with pixel clock > 162 MHz or h. blanking > 1023
001362.952: hdmi: HDMI:EDID preferred mode remained as CEA (16) 1920x1080p @ 60 Hz with pixel clock 148 MHz
001362.974: hdmi: HDMI: hotplug attached with HDMI support
001363.027: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
001363.060: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
001363.098: hdmi: HDMI:hdmi_get_state is deprecated, use hdmi_get_display_state instead
001363.157: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
001363.193: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
001363.231: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
001363.266: clock: clock_set_clock: dst: CLK_ISP, source: XOSC, div: 0.000000
001363.306: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 1.000000
001363.336: clock: clock_set_clock: dst: CLK_VEC, source: XOSC, div: 0.000000
001363.541: clock: clock_set_clock: dst: CLK_HSM, source: PLLD_PER, div: 5.000000
001364.579: clock: Set PLLH_VCO to 1008000000
001365.776: hdmi: HDMI: power_on to CEA mode 1080p60
001366.841: clock: clock_set_clock: dst: CLK_HSM, source: PLLD_PER, div: 3.054687
001367.880: clock: Set PLLH_VCO to 1485000000
001368.999: hdmi: HDMI: Action callback added to queue to happen at frame 2
001369.021: hdmi: HDMI: Action stop_3d_mode added to queue to happen at frame 2
001369.044: hdmi: HDMI: Action unmute added to queue to happen at frame 3
001419.227: clock: clock_set_clock: dst: CLK_TSENS, source: XOSC, div: 9.600000
001419.717: *** Restart logging
001420.815: Read command line from file 'cmdline.txt'
boot=/dev/mmcblk0p1 disk=/dev/mmcblk0p2 quiet
001420.989: clock: clock_set_clock: dst: CLK_UART, source: PLLD_PER, div: 10.416670
001431.256: Can't find 'kernel7.img' on boot device - rc 2
001431.319: Loading 'kernel.img' from SD card
001737.504: Kernel trailer DTOK property says yes
001737.654: Loading 'bcm2710-rpi-3-b.dtb' from SD card
001751.003: dtdebug: /aliases:i2c_vc=i2c0
001754.714: dtdebug: /__symbols__:i2c_vc=i2c0
001757.717: dtdebug: /__overrides__:i2c_vc=i2c0
001763.415: dtdebug: /__overrides__:i2c_vc_baudrate=i2c0_baudrate
001765.887: dtdebug: /aliases:i2c=i2c1
001769.673: dtdebug: /__symbols__:i2c=i2c1
001772.737: dtdebug: /__overrides__:i2c=i2c1
001775.232: dtdebug: /aliases:i2c_arm=i2c1
001779.021: dtdebug: /__symbols__:i2c_arm=i2c1
001782.120: dtdebug: /__overrides__:i2c_arm=i2c1
001787.958: dtdebug: /__overrides__:i2c_baudrate=i2c1_baudrate
001793.844: dtdebug: /__overrides__:i2c_arm_baudrate=i2c1_baudrate
001793.875: dtparam: uart0_clkrate=48000000
001795.698: dtdebug: Found override uart0_clkrate
001795.741: dtdebug: override uart0_clkrate: cell target clock-frequency @ offset 0 (size 4)
001815.510: Loaded overlay 'hifiberry-digi'
001815.562: dtdebug: Found fragment 0 (offset 36)
001816.689: dtdebug: merge_fragment(/sound,/fragment@0/__overlay__)
001816.714: dtdebug: +prop(compatible)
001818.191: dtdebug: +prop(i2s-controller)
001820.011: dtdebug: +prop(status)
001821.559: dtdebug: merge_fragment() end
001821.610: dtdebug: Found fragment 1 (offset 168)
001825.583: dtdebug: merge_fragment(/soc/i2s@7e203000,/fragment@1/__overlay__)
001825.608: dtdebug: +prop(status)
001826.727: dtdebug: merge_fragment() end
001826.776: dtdebug: Found fragment 2 (offset 244)
001832.385: dtdebug: merge_fragment(/soc/i2c@7e804000,/fragment@2/__overlay__)
001832.407: dtdebug: +prop(#address-cells)
001833.336: dtdebug: +prop(#size-cells)
001834.271: dtdebug: +prop(status)
001837.890: dtdebug: merge_fragment(/soc/i2c@7e804000/wm8804@3b,/fragment@2/__overlay__/wm8804@3b)
001837.925: dtdebug: +prop(#sound-dai-cells)
001838.954: dtdebug: +prop(compatible)
001839.861: dtdebug: +prop(reg)
001840.823: dtdebug: +prop(status)
001841.808: dtdebug: merge_fragment() end
001841.833: dtdebug: merge_fragment() end
001890.155: dtparam: arm_freq=1200000000
001892.108: dtdebug: Found override arm_freq
001892.149: dtdebug: override arm_freq: cell target clock-frequency @ offset 0 (size 4)
001899.268: dtdebug: override arm_freq: cell target clock-frequency @ offset 0 (size 4)
001906.473: dtdebug: override arm_freq: cell target clock-frequency @ offset 0 (size 4)
001914.165: dtdebug: override arm_freq: cell target clock-frequency @ offset 0 (size 4)
001921.524: dtparam: core_freq=400000000
001923.572: dtdebug: Found override core_freq
001923.614: dtdebug: override core_freq: cell target clock-frequency @ offset 0 (size 4)
001929.339: dtparam: cache_line_size=64
001931.286: dtdebug: Found override cache_line_size
001931.328: dtdebug: override cache_line_size: cell target cache-line-size @ offset 0 (size 4)
001936.567: dtdebug: delete_node(/hat)
001945.225: Device tree loaded to 2efec800 (size 3721)
001945.731: clock: Set PLLB_VCO to 1200000000
001945.848: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
001945.927: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 4.000000
001945.987: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.000000
001946.058: clock: Set PLLA_VCO to 2000000000
001946.164: clock: clock_set_clock: dst: CLK_V3D, source: PLLA_CORE, div: 4.000000
001946.225: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
001946.287: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 4.000000
001947.730: gpioman: gpioman_get_pin_num: pin SDCARD_CONTROL_POWER not defined
001947.822: clock: Set PLLB_VCO to 640000000
001947.895: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
001947.926: clock: Set PLLB_VCO to 1200000000
001947.997: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
001948.036: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 1.000000
001948.071: clock: clock_set_clock: dst: CLK_ARM, source: XOSC, div: 0.000000
001948.097: clock: Set PLLB_VCO to 1200000000
001948.213: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
003531.066: vchiq_core: vchiq_init_state: slot_zero = 0xee880000, is_master = 1
003534.798: hdmi: HDMI:hdmi_get_state is deprecated, use hdmi_get_display_state instead
003538.643: gpioman: gpioman_get_pin_num: pin LEDS_RUNNING not defined
003538.667: gpioman: gpioman_get_pin_num: pin LEDS_NAND_ACTIVITY not defined
003538.690: gpioman: gpioman_get_pin_num: pin LEDS_USB_ACTIVITY not defined
003538.711: gpioman: gpioman_get_pin_num: pin LEDS_FATAL_ERROR not defined
003538.734: gpioman: gpioman_get_pin_num: pin LEDS_APP_OK not defined
003538.756: gpioman: gpioman_get_pin_num: pin LEDS_APP_FAILED not defined
003538.777: gpioman: gpioman_get_pin_num: pin LEDS_HDCP_AUTH not defined
003538.800: gpioman: gpioman_get_pin_num: pin LEDS_HDCP_UNAUTH not defined
003538.823: gpioman: gpioman_get_pin_num: pin LEDS_HDMI_ON not defined
003538.845: gpioman: gpioman_get_pin_num: pin LEDS_DVI_ON not defined
003538.868: gpioman: gpioman_get_pin_num: pin LEDS_HDMI_HPD_UP not defined
003538.889: gpioman: gpioman_get_pin_num: pin LEDS_REMOTE_CONTROL not defined
003538.911: gpioman: gpioman_get_pin_num: pin LEDS_ARM_CONTROLLED not defined
003539.296: TV service:host side not connected, dropping notification 0x00000002, 0x00000001, 0x00000010
003938.753: clock: Set PLLB_VCO to 2400000000
003938.833: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
003938.918: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
003938.962: clock: Set PLLC_VCO to 2400000000
003939.032: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 3.000000
003939.075: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
003939.158: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 3.333333
003939.225: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 3.333333
003939.251: clock: Set PLLA_VCO to 2400000000
005680.070: clock: Set PLLB_VCO to 1200000000
005680.130: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
005680.175: clock: Set PLLC_VCO to 2000000000
005680.241: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 4.000000
005680.300: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.000000
005680.368: clock: Set PLLA_VCO to 2000000000
005680.475: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
005680.534: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 4.000000
005780.696: clock: Set PLLB_VCO to 2400000000
005780.773: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
005780.853: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
005780.896: clock: Set PLLC_VCO to 2400000000
005780.967: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 3.000000
005781.009: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
005781.092: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 3.333333
005781.158: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 3.333333
005781.186: clock: Set PLLA_VCO to 2400000000
010590.421: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 1.000000
010590.450: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
010590.477: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
010590.534: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
010590.642: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 1.000000
010590.667: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
010590.696: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
010590.745: clock: clock_set_clock: dst: CLK_H264, source: XOSC, div: 0.000000
010601.291: hdmi: HDMI:Setting property pixel clock type to PAL
010601.350: hdmi: HDMI: power_on to CEA mode 1080p60
010601.379: hdmi: HDMI: Action detach added to queue to happen at frame 550
010601.394: hdmi: HDMI: Action change_mode added to queue to happen at frame 550
010601.409: hdmi: HDMI: Action attach added to queue to happen at frame 550
010601.424: hdmi: HDMI: Action start_mode added to queue to happen at frame 550
010601.439: hdmi: HDMI: Action callback added to queue to happen at frame 552
010601.454: hdmi: HDMI: Action stop_3d_mode added to queue to happen at frame 552
010601.468: hdmi: HDMI: Action unmute added to queue to happen at frame 553
010870.078: hdmi: HDMI:Setting property pixel clock type to PAL
010870.130: hdmi: HDMI: power_on to CEA mode 1080p60
010870.161: hdmi: HDMI: Action detach added to queue to happen at frame 567
010870.177: hdmi: HDMI: Action change_mode added to queue to happen at frame 567
010870.191: hdmi: HDMI: Action attach added to queue to happen at frame 567
010870.206: hdmi: HDMI: Action start_mode added to queue to happen at frame 567
010870.222: hdmi: HDMI: Action callback added to queue to happen at frame 569
010870.236: hdmi: HDMI: Action stop_3d_mode added to queue to happen at frame 569
010870.251: hdmi: HDMI: Action unmute added to queue to happen at frame 570
014680.173: clock: Set PLLB_VCO to 1200000000
014680.245: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
014680.298: clock: Set PLLC_VCO to 2000000000
014680.373: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 4.000000
014680.445: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.000000
014680.522: clock: Set PLLA_VCO to 2000000000
014680.634: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
014680.699: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 4.000000
031080.816: clock: Set PLLB_VCO to 2400000000
031080.898: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
031080.985: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
031081.031: clock: Set PLLC_VCO to 2400000000
031081.102: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 3.000000
031081.146: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
031081.230: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 3.333333
031081.298: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 3.333333
031081.324: clock: Set PLLA_VCO to 2400000000
034680.180: clock: Set PLLB_VCO to 1200000000
034680.245: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
034680.294: clock: Set PLLC_VCO to 2000000000
034680.362: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 4.000000
034680.423: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.000000
034680.495: clock: Set PLLA_VCO to 2000000000
034680.606: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
034680.667: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 4.000000
039380.930: clock: Set PLLB_VCO to 2400000000
039381.026: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
039381.125: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
039381.172: clock: Set PLLC_VCO to 2400000000
039381.255: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 3.000000
039381.295: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
039381.391: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 3.333333
039381.459: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 3.333333
039381.494: clock: Set PLLA_VCO to 2400000000
044680.159: clock: Set PLLB_VCO to 1200000000
044680.225: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
044680.271: clock: Set PLLC_VCO to 2000000000
044680.339: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 4.000000
044680.401: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.000000
044680.475: clock: Set PLLA_VCO to 2000000000
044680.582: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
044680.646: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 4.000000
048890.916: clock: Set PLLB_VCO to 2400000000
048891.019: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
048891.127: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
048891.177: clock: Set PLLC_VCO to 2400000000
048891.264: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 3.000000
048891.320: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
048891.419: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 3.333333
048891.489: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 3.333333
048891.533: clock: Set PLLA_VCO to 2400000000
049680.217: clock: Set PLLB_VCO to 1200000000
049680.285: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
049680.342: clock: Set PLLC_VCO to 2000000000
049680.412: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 4.000000
049680.474: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.000000
049680.545: clock: Set PLLA_VCO to 2000000000
049680.654: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
049680.718: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 4.000000
132181.129: clock: Set PLLB_VCO to 2400000000
132181.224: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
132181.308: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
132181.358: clock: Set PLLC_VCO to 2400000000
132181.434: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 3.000000
132181.478: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
132181.561: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 3.333333
132181.631: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 3.333333
132181.663: clock: Set PLLA_VCO to 2400000000
134680.402: clock: Set PLLB_VCO to 1200000000
134680.471: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
134680.520: clock: Set PLLC_VCO to 2000000000
134680.588: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 4.000000
134680.654: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.000000
134680.758: clock: Set PLLA_VCO to 2000000000
134680.864: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
134680.927: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 4.000000
392635.057: clock: Set PLLB_VCO to 2400000000
392635.167: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
392635.258: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
392635.308: clock: Set PLLC_VCO to 2400000000
392635.383: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 3.000000
392635.428: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
392635.520: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 3.333333
392635.585: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 3.333333
392635.620: clock: Set PLLA_VCO to 2400000000
397334.380: clock: Set PLLB_VCO to 1200000000
397334.450: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
397334.507: clock: Set PLLC_VCO to 2000000000
397334.580: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 4.000000
397334.640: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.000000
397334.714: clock: Set PLLA_VCO to 2000000000
397334.825: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
397334.891: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 4.000000
456735.167: clock: Set PLLB_VCO to 2400000000
456735.264: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
456735.353: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
456735.398: clock: Set PLLC_VCO to 2400000000
456735.472: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 3.000000
456735.513: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
456735.600: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 3.333333
456735.669: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 3.333333
456735.697: clock: Set PLLA_VCO to 2400000000
462334.538: clock: Set PLLB_VCO to 1200000000
462334.606: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
462334.656: clock: Set PLLC_VCO to 2000000000
462334.722: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 4.000000
462334.785: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.000000
462334.860: clock: Set PLLA_VCO to 2000000000
462334.971: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
462335.034: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 4.000000
462935.231: clock: Set PLLB_VCO to 2400000000
462935.317: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
462935.408: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
462935.462: clock: Set PLLC_VCO to 2400000000
462935.532: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 3.000000
462935.580: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.800000
462935.669: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 3.333333
462935.744: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 3.333333
462935.771: clock: Set PLLA_VCO to 2400000000
467334.527: clock: Set PLLB_VCO to 1200000000
467334.595: clock: clock_set_clock: dst: CLK_ARM, source: PLLB_ARM, div: 1.000000
467334.645: clock: Set PLLC_VCO to 2000000000
467334.719: clock: clock_set_clock: dst: CLK_VPU, source: PLLC_CORE0, div: 4.000000
467334.789: clock: clock_set_clock: dst: CLK_EMMC, source: PLLC_PER, div: 4.000000
467334.858: clock: Set PLLA_VCO to 2000000000
467334.969: clock: clock_set_clock: dst: CLK_H264, source: PLLA_CORE, div: 4.000000
467335.029: clock: clock_set_clock: dst: CLK_ISP, source: PLLA_CORE, div: 4.000000
OpenELEC:~ #

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